Processing devices, such as central processing units (CPUs), often implement one or more timers to control operations or to provide periodic stimuli during normal operations. However, when a processing device enters a debug mode, improper control of these timers can lead to error states in the operation of the processing device. In order to reduce the risk of improper operation, some processing devices implement a scheme whereby all timers are disabled by default while in a debug mode. While this scheme has the potential to reduce or eliminate certain undesirable timer-related operations, such as an unintended reset caused by a watchdog timer that was not timely refreshed, certain instructions being debugged may make use of other timers and thus the debugging of these instructions while all timers are disabled can result in an inaccurate debug analysis. Accordingly, an improved technique for controlling timers in a processing device would be advantageous.